tc4011bp/bf/bft 2012-02-29 1 toshiba cmos digital integrat ed ci rcuit silicon monolithic tc4011bp,tc4011bf, tc4011bft tc4011b quad 2 input nand gate the tc4011b is 2-input positive logic nand gate respectively. since all the outputs of these gates are provided with the inverters as buffers, the input/ou tput characteristics have been improved and the variation of pr opagation delay time due to the increase in load capacity is kept down to the minimum. pin assignment logic diagram tc4011bp tc4011bf tc4011bft weight dip14-p-300-2.54 : 0.96 g (typ.) sop14-p-300-1.27a : 0.18 g (typ.) tssop14-p-0044-0.65a : 0.06 g (typ.) v dd 9 b4 x4 8 14 13 12 11 10 1 2 3 4 5 6 7 b2 a2 v ss b3 a 3 (top view) b1 x1 a1 x2 a 4 x3 a x = ba ? x b
tc4011bp/bf/bft 2012-02-29 2 absolute maximum ratings (note) characteristics symbol rating unit dc supply voltage v dd v ss ? 0.5 to v ss + 20 v input voltage v in v ss ? 0.5 to v dd + 0.5 v output voltage v out v ss ? 0.5 to v dd + 0.5 v dc input current i in 10 ma power dissipation p d 300 (dip)/180 (soic) mw operating temperature range t opr ? 40 to 85 c storage temperature range t stg ? 65 to 150 c note: exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in ic performance or even destruction. using continuously under heavy loads (e.g. the app lication of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temper ature/current/voltage, etc. ) are within the absolute maximum ratings and the operating ranges. please design the appropriate reliability upon reviewing the toshiba semiconductor reliability handbook (?handling precautions?/?derating concept and methods?) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). operating ranges (v ss = 0 v) (note) characteristics symbol test condition min typ. max unit dc supply voltage v dd D 3 D 18 v input voltage v in D 0 D v dd v note: the operating ranges must be maintained to ensure the normal oper ation of the device. unused inputs must be tied to either v dd or v ss .
tc4011bp/bf/bft 2012-02-29 3 static electrical characteristics (v ss = 0 v) test condition 40c 25c 85c characteristics symbol v dd (v) min max min typ. max min max unit high-level output voltage v oh |i out | < 1 a v in = v ss , v dd 5 10 15 4.95 9.95 14.95 ? ? ? 4.95 9.95 14.95 5.00 10.00 15.00 ? ? ? 4.95 9.95 14.95 ? ? ? v low-level output voltage v ol |i out | < 1 a v in = v ss , v dd 5 10 15 ? ? ? 0.05 0.05 0.05 ? ? ? 0.00 0.00 0.00 0.05 0.05 0.05 ? ? ? 0.05 0.05 0.05 v v oh = 4.6 v v oh = 2.5 v v oh = 9.5 v v oh = 13.5 v 5 5 10 15 0.61 2.50 1.50 4.00 ? ? ? ? 0.51 2.10 1.30 3.40 1.0 4.0 2.2 9.0 ? ? ? ? 0.42 1.70 1.10 2.80 ? ? ? ? output high current i oh v in = v ss , v dd ma v ol = 0.4 v v ol = 0.5 v v ol = 1.5 v 5 10 15 0.61 1.50 4.00 ? ? ? 0.51 1.30 3.40 1.2 3.2 12.0 ? ? ? 0.42 1.10 2.80 ? ? ? output low current i ol v in = v dd ma v out = 0.5 v v out = 1.0 v v out = 1.5 v 5 10 15 3.5 7.0 11.0 ? ? ? 3.5 7.0 11.0 2.75 5.50 8.25 ? ? ? 3.5 7.0 11.0 ? ? ? input high voltage v ih |i out | < 1 a v v out = 4.5 v v out = 9.0 v v out = 13.5 v 5 10 15 ? ? ? 1.5 3.0 4.0 ? ? ? 2.25 4.50 6.75 1.5 3.0 4.0 ? ? ? 1.5 3.0 4.0 input low voltage v il |i out | < 1 a v ?h? level i ih v ih = 18 v 18 ? 0.1 ? 10 5 0.1 ? 1.0 input current ?l? level i il v il = 0 v 18 ? 0.1 ? 10 5 0.1 ? 1.0 a quiescent supply current i dd v in = v ss , v dd (note) 5 10 15 ? ? ? 0.25 0.50 1.00 ? ? ? 0.001 0.001 0.002 0.25 0.50 1.00 ? ? ? 7.5 15.0 30.0 a note: all valid input combinations.
tc4011bp/bf/bft 2012-02-29 4 dynamic electrical characteristics (ta = 25c, v ss = 0 v, c l = 50 pf) test condition characteristics symbol v dd (v) min typ. max unit output transition time t tlh D 5 10 15 D D D 70 35 30 200 100 80 ns output transition time t thl D 5 10 15 D D D 70 35 30 200 100 80 ns propagation delay time t plh D 5 10 15 D D D 65 30 25 200 100 80 ns propagation delay time t phl D 5 10 15 D D D 65 30 25 200 100 80 ns input capacitance c in D D 5 7.5 pf circuit and waveform for measureme nt of dynamic characteristics circuit waveform output input 20 ns 20 ns 50% 10% 90% t plh t phl 50% 10% 90% 50% 10% 90% 50% 10% 90% t tlh t thl v dd output v ss input p.g. c l = 50 pf
tc4011bp/bf/bft 2012-02-29 5 package dimensions weight: 0.96 g (typ.)
tc4011bp/bf/bft 2012-02-29 6 package dimensions weight: 0.18 g (typ.)
tc4011bp/bf/bft 2012-02-29 7 package dimensions weight: 0.06 g (typ.)
tc4011bp/bf/bft 2012-02-29 8 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (collect ively "toshiba"), reserve the right to make changes to the in formation in this document, and related hardware, software and systems (collectively "product") without notice. ? this document and any information herein may not be reproduc ed without prior written permission from toshiba. even with toshiba's written permission, reproduc tion is permissible only if reproduction is without alteration/omission. ? though toshiba works continually to improve product's quality and reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for prov iding adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a ma lfunction or failure of product could cause loss of human life, b odily injury or damage to property, including data loss or corruption. before customers use the product, create designs including the product, or incorporate the product into their own applications, cu stomers must also refer to and comply with (a) the latest versions of all relevant toshiba information, including without limitation, this document, the specifications, the data sheets and application notes for product and the precautions and condi tions set forth in the "toshiba semiconductor reliability handbook" and (b) the instructions for the application with which the product will be us ed with or for. customers are solely responsible for all aspe cts of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this product in such design or applications; (b) eval uating and determining the applicability of any info rmation contained in this document, or in c harts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operatin g parameters for such designs and applications. toshiba assumes no liability for customers' product design or applications. ? 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